1. Field of the Invention
The present invention relates generally to methods for fabricating semiconductor devices, and more particularly, to a method for fabricating a printed circuit board having capacitance components.
2. Description of Related Art
As electronic products have a trend towards high function and high speed, passive components, such as resistors, capacitors or inductors, have to be integrated into semiconductor packages for enhancing or stabilizing the electrical functions of the electronic products.
As shown in FIG. 1, passive components 12 are generally provided in a region outside semiconductor chip mounting regions so as not to adversely affect electrical connection between active components such as semiconductor chips 11 and a plurality of solder pads (not shown). However, the presence of the passive components 12 decreases the flexibility of circuit layout on the printed circuit board 1, and the positions of the solder pads limit the number of the passive components 12, thereby adversely affecting the integration of semiconductor devices. Moreover, the number of the passive components 12 increases with the requirement of semiconductor devices for high performance. Accordingly, the printed circuit board 1 must accommodate a plurality of semiconductor chips 11 and plenty of passive components 12. As a result, the package size increases and the package cannot meet the development trend of being lighter, thinner, shorter and smaller.
Therefore, printed circuit board structures having embedded active components and passive components are developed for the sake of miniaturization with a view to getting in line with the trend towards lighter, thinner, shorter and smaller electronic products.
FIGS. 2A to 2H are sectional views showing a conventional method for fabricating a printed circuit board having embedded passive components.
As shown in FIG. 2A, a CCL (Copper Clad Laminate) core board 21 with surfaces thereof covered with a thin metal layer 21a is provided, and at least one through hole 210 is formed to penetrate the core board 21.
As shown in FIGS. 2A and 2B, a conductive layer 22 is formed on the thin metal layer 21a and on the wall of the through hole 210.
As shown in FIG. 2C, a metal layer 23 is plated to the conductive layer 22 on the thin metal layer 21a and in the through hole 210 such that the through hole 210 becomes a conductive through hole 231.
As shown in FIG. 2D, a filling material 24 made of resin fills the conductive through hole 231.
As shown in FIG. 2E, the metal layer 23, the conductive layer 22 and the thin metal layer 21a are patterned so as to form a first wiring layer 25a on the core board 21, wherein the first wiring layer 25a comprises a plurality of first electrode plates 251 and the conductive through hole 231 is electrically connected to the first wiring layer 25a. The patterning process to form the wiring layer 25 is well known in the art and detailed description thereof is omitted herein.
As shown in FIG. 2F, a high dielectric material layer 26 is formed on the core board 21 and the first wiring layer 25a. 
As shown in FIG. 2G, a second wiring layer 25b is formed on the high dielectric material layer 26, wherein the second wiring layer 25b comprises a plurality of second electrode plates 252 corresponding in position to the first electrode plates 251, respectively, such that the first electrode plates 251, the high dielectric material layer 26 and the second electrode plates 252 together form capacitors 20.
As shown in FIG. 2H, a build-up structure 27 is formed on the second wiring layer 25b and the high dielectric material layer 26, wherein the build-up structure 27 comprises at least a dielectric layer 271, a third wiring layer 25c formed on the dielectric layer 271, and a plurality of conductive vias 273 formed in the dielectric layer 271 and electrically connected to the third wiring layer 25c and the second wiring layer 25b. The build-up structure 27 further comprises a plurality of electrical contact pads 274 electrically connected to the third wiring layer 25c. A solder mask layer 28 is formed on the build-up structure 27. A plurality of openings 280 corresponding in position to the electrical contact pads 274, respectively, are formed in the solder mask layer 28 for exposing the electrical contact pads 274, respectively.
However, in the conventional printed circuit board having embedded capacitance components, since the high dielectric material layer 26 has a high content of ceramic filler, it results in poor flow of the high dielectric material; if the first wiring layer 25a is too thick or the thickness of the high dielectric material layer 26 decreases, space between circuits of the first wiring layer 25a cannot be completely filled with the high dielectric material, thereby resulting in voids or depressions.
Currently, a high Dk thin core layer can also be used as a core board of a printed circuit board structure, but the high Dk dielectric layer of the high Dk thin core layer has a thickness of less than 30 μm and does not contain glass fiber, therefore, after circuits of the printed circuit board structure are finished, the high Dk thin core layer that lacks support from copper foil is easy to crack.
Therefore, it is imperative to provide a method for fabricating a printed circuit board having capacitance components so as to overcome the above-described drawbacks.